The portable gnu assembler.
as [-a[cdhlns][=file]] [--alternate] [-D] [--debug-prefix-map old=new] [--defsym sym=val] [-f] [-g] [--gstabs] [--gstabs+] [--gdwarf-2] [--help] [-I dir] [-J] [-K] [-L] [--listing-lhs-width=\s-1NUM\s0] [--listing-lhs-width2=\s-1NUM\s0] [--listing-rhs-width=\s-1NUM\s0] [--listing-cont-lines=\s-1NUM\s0] [--keep-locals] [-o objfile] [-R] [--reduce-memory-overheads] [--statistics] [-v] [-version] [--version] [-W] [--warn] [--fatal-warnings] [-w] [-x] [-Z] [@\s-1FILE\s0] [--target-help] [target-options] [--|files ...]
Target Alpha options:
[-mcpu] [-mdebug | -no-mdebug] [-relax] [-g] [-Gsize] [-F] [-32addr]
Target \s-1ARC\s0 options:
[-marc[5|6|7|8]] [-EB|-EL]
Target \s-1ARM\s0 options:
[-mcpu=processor[+extension...]]
[-march=architecture[+extension...]]
[-mfpu=floating-point-format]
[-mfloat-abi=abi]
[-meabi=ver]
[-mthumb]
[-EB|-EL]
[-mapcs-32|-mapcs-26|-mapcs-float|
-mapcs-reentrant]
[-mthumb-interwork] [-k]
Target \s-1CRIS\s0 options:
[--underscore | --no-underscore] [--pic] [-N] [--emulation=criself | --emulation=crisaout] [--march=v0_v10 | --march=v10 | --march=v32 | --march=common_v10_v32]
Target D10V options:
[-O]
Target D30V options:
[-O|-n|-N]
Target i386 options:
[--32|--64] [-n] [-march=\s-1CPU\s0] [-mtune=\s-1CPU\s0]
Target i960 options:
[-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB|
-AKC|-AMC]
[-b] [-no-relax]
Target \s-1IA-64\s0 options:
[-mconstant-gp|-mauto-pic] [-milp32|-milp64|-mlp64|-mp64] [-mle|mbe] [-mtune=itanium1|-mtune=itanium2] [-munwind-check=warning|-munwind-check=error] [-mhint.b=ok|-mhint.b=warning|-mhint.b=error] [-x|-xexplicit] [-xauto] [-xdebug]
Target \s-1IP2K\s0 options:
[-mip2022|-mip2022ext]
Target M32C options:
[-m32c|-m16c]
Target M32R options:
[--m32rx|--[no-]warn-explicit-parallel-conflicts| --W[n]p]
Target M680X0 options:
[-l] [-m68000|-m68010|-m68020|...]
Target M68HC11 options:
[-m68hc11|-m68hc12|-m68hcs12] [-mshort|-mlong] [-mshort-double|-mlong-double] [--force-long-branches] [--short-branches] [--strict-direct-mode] [--print-insn-syntax] [--print-opcodes] [--generate-example]
Target \s-1MCORE\s0 options:
[-jsri2bsr] [-sifilter] [-relax] [-mcpu=[210|340]]
Target \s-1MIPS\s0 options:
[-nocpp] [-EL] [-EB] [-O[optimization level]] [-g[debug level]] [-G num] [-KPIC] [-call_shared] [-non_shared] [-xgot [-mvxworks-pic] [-mabi=\s-1ABI\s0] [-32] [-n32] [-64] [-mfp32] [-mgp32] [-march=\s-1CPU\s0] [-mtune=\s-1CPU\s0] [-mips1] [-mips2] [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2] [-mips64] [-mips64r2] [-construct-floats] [-no-construct-floats] [-trap] [-no-break] [-break] [-no-trap] [-mfix7000] [-mno-fix7000] [-mips16] [-no-mips16] [-msmartmips] [-mno-smartmips] [-mips3d] [-no-mips3d] [-mdmx] [-no-mdmx] [-mdsp] [-mno-dsp] [-mdspr2] [-mno-dspr2] [-mmt] [-mno-mt] [-mdebug] [-no-mdebug] [-mpdr] [-mno-pdr]
Target \s-1MMIX\s0 options:
[--fixed-special-register-names] [--globalize-symbols] [--gnu-syntax] [--relax] [--no-predefined-symbols] [--no-expand] [--no-merge-gregs] [-x] [--linker-allocated-gregs]
Target \s-1PDP11\s0 options:
[-mpic|-mno-pic] [-mall] [-mno-extensions] [-mextension|-mno-extension] [-mcpu] [-mmachine]
Target picoJava options:
[-mb|-me]
Target PowerPC options:
[-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|
-m403|-m405|-mppc64|-m620|-mppc64bridge|-mbooke|
-mbooke32|-mbooke64]
[-mcom|-many|-maltivec] [-memb]
[-mregnames|-mno-regnames]
[-mrelocatable|-mrelocatable-lib]
[-mlittle|-mlittle-endian|-mbig|-mbig-endian]
[-msolaris|-mno-solaris]
Target \s-1SPARC\s0 options:
[-Av6|-Av7|-Av8|-Asparclet|-Asparclite
-Av8plus|-Av8plusa|-Av9|-Av9a]
[-xarch=v8plus|-xarch=v8plusa] [-bump]
[-32|-64]
Target \s-1TIC54X\s0 options: [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf] [-merrors-to-file <filename>|-me <filename>]
Target Z80 options:
[-z80] [-r800] [ -ignore-undocumented-instructions] [-Wnud] [ -ignore-unportable-instructions] [-Wnup] [ -warn-undocumented-instructions] [-Wud] [ -warn-unportable-instructions] [-Wup] [ -forbid-undocumented-instructions] [-Fud] [ -forbid-unportable-instructions] [-Fup]
Target Xtensa options: [--[no-]text-section-literals] [--[no-]absolute-literals] [--[no-]target-align] [--[no-]longcalls] [--[no-]transform] [--rename-section oldname=newname]
\s-1GNU\s0 as is really a family of assemblers. If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you should find a fairly similar environment when you use it on another architecture. Each version has much in common with the others, including object file formats, most assembler directives (often called pseudo-ops) and assembler syntax.
as is primarily intended to assemble the output of the \s-1GNU\s0 C compiler \*(C`gcc\*(C' for use by the linker \*(C`ld\*(C'. Nevertheless, we've tried to make as assemble correctly everything that other assemblers for the same machine would assemble. Any exceptions are documented explicitly. This doesn't mean as always uses the same syntax as another assembler for the same architecture; for example, we know of several incompatible versions of 680x0 assembly language syntax.
Each time you run as it assembles exactly one source program. The source program is made up of one or more files. (The standard input is also a file.)
You give as a command line that has zero or more input file names. The input files are read (from left file name to right). A command line argument (in any position) that has no special meaning is taken to be an input file name.
If you give as no file names it attempts to read one input file from the as standard input, which is normally your terminal. You may have to type ctl-D to tell as there is no more program to assemble.
Use -- if you need to explicitly name the standard input file in your command line.
If the source is empty, as produces a small, empty object file.
as may write warnings and error messages to the standard error file (usually your terminal). This should not happen when a compiler runs as automatically. Warnings report an assumption made so that as could keep assembling a flawed program; errors report a grave problem that stops the assembly.
If you are invoking as via the \s-1GNU\s0 C compiler, you can use the -Wa option to pass arguments through to the assembler. The assembler arguments must be separated from each other (and the -Wa) by commas. For example:
gcc -c -g -O -Wa,-alh,-L file.c
This passes two options to the assembler: -alh (emit a listing to standard output with high-level and assembly source) and -L (retain local symbols in the symbol table).
Usually you do not need to use this -Wa mechanism, since many compiler command-line options are automatically passed to the assembler by the compiler. (You can call the \s-1GNU\s0 compiler driver with the -v option to see precisely what options it passes to each compilation pass, including the assembler.)
Read command-line options from file. The options read are inserted in place of the original @file option. If file does not exist, or cannot be read, then the option will be treated literally, and not removed. Options in file are separated by whitespace. A whitespace character may be included in an option by surrounding the entire option in either single or double quotes. Any character (including a backslash) may be included by prefixing the character to be included with a backslash. The file may itself contain additional @file options; any such options will be processed recursively.
Turn on listings, in any of a variety of ways:
omit false conditionals
omit debugging directives
include high-level source
include assembly
include macro expansions
omit forms processing
include symbols
set the name of the listing file
You may combine these options; for example, use -aln for assembly listing without forms processing. The =file option, if used, must be the last one. By itself, -a defaults to -ahls.
Begin in alternate macro mode.
Ignored. This option is accepted for script compatibility with calls to other assemblers.
When assembling files in directory old, record debugging information describing them as in new instead.
Define the symbol sym to be value before assembling the input file. value must be an integer constant. As in C, a leading 0x indicates a hexadecimal value, and a leading 0 indicates an octal value. The value of the symbol can be overridden inside a source file via the use of a \*(C`.set\*(C' pseudo-op.
\*(L"fast\*(R"---skip whitespace and comment preprocessing (assume source is compiler output).
Generate debugging information for each assembler source line using whichever debug format is preferred by the target. This currently means either \s-1STABS\s0, \s-1ECOFF\s0 or \s-1DWARF2\s0.
Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it.
Generate stabs debugging information for each assembler line, with \s-1GNU\s0 extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program. This may help debugging assembler code. Currently the only \s-1GNU\s0 extension is the location of the current working directory at assembling time.
Generate \s-1DWARF2\s0 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note---this option is only supported by some targets, not all of them.
Print a summary of the command line options and exit.
Print a summary of all target specific options and exit.
Add directory dir to the search list for \*(C`.include\*(C' directives.
Don't warn about signed overflow.
Issue warnings when difference tables altered for long displacements.
Keep (in the symbol table) local symbols. These symbols start with system-specific local label prefixes, typically .L for \s-1ELF\s0 systems or L for traditional a.out systems.
Set the maximum width, in words, of the output data column for an assembler listing to number.
Set the maximum width, in words, of the output data column for continuation lines in an assembler listing to number.
Set the maximum width of an input source line, as displayed in a listing, to number bytes.
Set the maximum number of lines printed in a listing for a single line of input to number + 1.
Name the object-file output from as objfile.
Fold the data section into the text section. Set the default size of \s-1GAS\s0's hash tables to a prime number close to number. Increasing this value can reduce the length of time it takes the assembler to perform its tasks, at the expense of increasing the assembler's memory requirements. Similarly reducing this value can reduce the memory requirements at the expense of speed.
This option reduces \s-1GAS\s0's memory requirements, at the expense of making the assembly processes slower. Currently this switch is a synonym for --hash-size=4051, but in the future it may have other effects as well.
Print the maximum space (in bytes) and total time (in seconds) used by assembly.
Remove local absolute symbols from the outgoing symbol table.
Print the as version.
Print the as version and exit.
Suppress warning messages.
Treat warnings as errors.
Don't suppress warning messages or treat them as errors.
Ignored.
Ignored.
Generate an object file even after errors.
Standard input, or source files to assemble.
The following options are available when as is configured for an \s-1ARC\s0 processor.
This option selects the core processor variant.
Select either big-endian (-EB) or little-endian (-EL) output.
The following options are available when as is configured for the \s-1ARM\s0 processor family.
Specify which \s-1ARM\s0 processor variant is the target.
Specify which \s-1ARM\s0 architecture variant is used by the target.
Select which Floating Point architecture is the target.
Select which floating point \s-1ABI\s0 is in use.
Enable Thumb only instruction decoding.
Select which procedure calling convention is in use.
Select either big-endian (-EB) or little-endian (-EL) output.
Specify that the code has been generated with interworking between Thumb and \s-1ARM\s0 code in mind.
Specify that \s-1PIC\s0 code has been generated.
See the info pages for documentation of the CRIS-specific options.
The following options are available when as is configured for a D10V processor.
Optimize output by parallelizing instructions.
The following options are available when as is configured for a D30V processor.
Optimize output by parallelizing instructions.
Warn when nops are generated.
Warn when a nop after a 32-bit multiply instruction is generated.
The following options are available when as is configured for the Intel 80960 processor.
Specify which variant of the 960 architecture is the target.
Add code to collect statistics about branches taken.
Do not alter compare-and-branch instructions for long displacements; error if necessary.
The following options are available when as is configured for the Ubicom \s-1IP2K\s0 series.
Specifies that the extended \s-1IP2022\s0 instructions are allowed.
Restores the default behaviour, which restricts the permitted instructions to just the basic \s-1IP2022\s0 ones.
The following options are available when as is configured for the Renesas M32C and M16C processors.
Assemble M32C instructions.
Assemble M16C instructions (the default).
The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series.
Specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX.
Produce warning messages when questionable parallel constructs are encountered.
Do not produce warning messages when questionable parallel constructs are encountered.
The following options are available when as is configured for the Motorola 68000 series.
Shorten references to undefined symbols, to one word instead of two.
Specify what processor in the 68000 family is the target. The default is normally the 68020, but this can be changed at configuration time.
The target machine does (or does not) have a floating-point coprocessor. The default is to assume a coprocessor for 68020, 68030, and cpu32. Although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it's possible to do emulation of the coprocessor instructions with the main processor.
The target machine does (or does not) have a memory-management unit coprocessor. The default is to assume an \s-1MMU\s0 for 68020 and up.
For details about the \s-1PDP-11\s0 machine dependent features options, see PDP-11-Options.
Generate position-independent (or position-dependent) code. The default is -mpic.
Enable all instruction set extensions. This is the default.
Disable all instruction set extensions.
Enable (or disable) a particular instruction set extension.
Enable the instruction set extensions supported by a particular \s-1CPU\s0, and disable all other extensions.
Enable the instruction set extensions supported by a particular machine model, and disable all other extensions.
The following options are available when as is configured for a picoJava processor.
Generate \*(L"big endian\*(R" format output.
Generate \*(L"little endian\*(R" format output.
The following options are available when as is configured for the Motorola 68HC11 or 68HC12 series.
Specify what processor is the target. The default is defined by the configuration option when building the assembler.
Specify to use the 16-bit integer \s-1ABI\s0.
Specify to use the 32-bit integer \s-1ABI\s0.
Specify to use the 32-bit double \s-1ABI\s0.
Specify to use the 64-bit double \s-1ABI\s0.
Relative branches are turned into absolute ones. This concerns conditional branches, unconditional branches and branches to a sub routine.
Do not turn relative branches into absolute ones when the offset is out of range.
Do not turn the direct addressing mode into extended addressing mode when the instruction does not support direct addressing mode.
Print the syntax of instruction in case of error.
print the list of instructions with syntax and then exit.
print an example of instruction for each possible instruction and then exit. This option is only useful for testing as.
The following options are available when as is configured for the \s-1SPARC\s0 architecture:
Explicitly select a variant of the \s-1SPARC\s0 architecture. -Av8plus and -Av8plusa select a 32 bit environment. -Av9 and -Av9a select a 64 bit environment. -Av8plusa and -Av9a enable the \s-1SPARC\s0 V9 instruction set with UltraSPARC extensions.
For compatibility with the Solaris v9 assembler. These options are equivalent to -Av8plus and -Av8plusa, respectively.
Warn when the assembler switches to another architecture.
The following options are available when as is configured for the 'c54x architecture.
Enable extended addressing mode. All addresses and relocations will assume extended addressing (usually 23 bits).
Sets the \s-1CPU\s0 version being compiled for.
Redirect error output to a file, for broken systems which don't support such behaviour in the shell.
The following options are available when as is configured for a \s-1MIPS\s0 processor.
This option sets the largest size of an object that can be referenced implicitly with the \*(C`gp\*(C' register. It is only accepted for targets that use \s-1ECOFF\s0 format, such as a DECstation running Ultrix. The default value is 8.
Generate \*(L"big endian\*(R" format output.
Generate \*(L"little endian\*(R" format output.
Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level. -mips1 is an alias for -march=r3000, -mips2 is an alias for -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an alias for -march=r8000. -mips5, -mips32, -mips32r2, -mips64, and -mips64r2 correspond to generic \s-1MIPS\s0 V, \s-1MIPS32\s0, \s-1MIPS32\s0 Release 2, \s-1MIPS64\s0, and \s-1MIPS64\s0 Release 2 \s-1ISA\s0 processors, respectively.
Generate code for a particular \s-1MIPS\s0 cpu.
Schedule and tune for a particular \s-1MIPS\s0 cpu.
Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions.
Cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard \s-1ELF\s0 .stabs sections.
Control generation of \*(C`.pdr\*(C' sections.
The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI\s0, but these flags force a certain group of registers to be treated as 32 bits wide at all times. -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers.
Generate code for the \s-1MIPS\s0 16 processor. This is equivalent to putting \*(C`.set mips16\*(C' at the start of the assembly file. -no-mips16 turns off this option.
Enables the SmartMIPS extension to the \s-1MIPS32\s0 instruction set. This is equivalent to putting \*(C`.set smartmips\*(C' at the start of the assembly file. -mno-smartmips turns off this option.
Generate code for the \s-1MIPS-3D\s0 Application Specific Extension. This tells the assembler to accept \s-1MIPS-3D\s0 instructions. -no-mips3d turns off this option.
Generate code for the \s-1MDMX\s0 Application Specific Extension. This tells the assembler to accept \s-1MDMX\s0 instructions. -no-mdmx turns off this option.
Generate code for the \s-1DSP\s0 Release 1 Application Specific Extension. This tells the assembler to accept \s-1DSP\s0 Release 1 instructions. -mno-dsp turns off this option.
Generate code for the \s-1DSP\s0 Release 2 Application Specific Extension. This option implies -mdsp. This tells the assembler to accept \s-1DSP\s0 Release 2 instructions. -mno-dspr2 turns off this option.
Generate code for the \s-1MT\s0 Application Specific Extension. This tells the assembler to accept \s-1MT\s0 instructions. -mno-mt turns off this option.
The --no-construct-floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. By default --construct-floats is selected, allowing construction of these floating point constants.
This option causes as to emulate as configured for some other target, in all respects, including output format (choosing between \s-1ELF\s0 and \s-1ECOFF\s0 only), handling of pseudo-opcodes which may generate debugging information or store symbol table information, and default endianness. The available configuration names are: mipsecoff, mipself, mipslecoff, mipsbecoff, mipslelf, mipsbelf. The first two do not alter the default endianness from that of the primary target for which the assembler was configured; the others change the default to little- or big-endian as indicated by the b or l in the name. Using -EB or -EL will override the endianness selection in any case. This option is currently supported only when the primary target as is configured for is a \s-1MIPS\s0 \s-1ELF\s0 or \s-1ECOFF\s0 target. Furthermore, the primary target or others specified with --enable-targets=... at configuration time must include support for the other format, if both are to be available. For example, the Irix 5 configuration includes support for both. Eventually, this option will support more configurations, with more fine-grained control over the assembler's behavior, and will be supported for more processors.
as ignores this option. It is accepted for compatibility with the native tools.
Control how to deal with multiplication overflow and division by zero. --trap or --no-break (which are synonyms) take a trap exception (and only work for Instruction Set Architecture level 2 and higher); --break or --no-trap (also synonyms, and the default) take a break exception.
When this option is used, as will issue a warning every time it generates a nop instruction from a macro.
The following options are available when as is configured for an MCore processor.
Enable or disable the \s-1JSRI\s0 to \s-1BSR\s0 transformation. By default this is enabled. The command line option -nojsri2bsr can be used to disable it.
Enable or disable the silicon filter behaviour. By default this is disabled. The default can be overridden by the -sifilter command line option.
Alter jump instructions for long displacements.
Select the cpu type on the target hardware. This controls which instructions can be assembled.
Assemble for a big endian target.
Assemble for a little endian target.
See the info pages for documentation of the MMIX-specific options.
The following options are available when as is configured for an Xtensa processor.
With --text-section-literals, literal pools are interspersed in the text section. The default is --no-text-section-literals, which places literals in a separate section in the output file. These options only affect literals referenced via PC-relative \*(C`L32R\*(C' instructions; literals for absolute mode \*(C`L32R\*(C' instructions are handled separately.
Indicate to the assembler whether \*(C`L32R\*(C' instructions use absolute or PC-relative addressing. The default is to assume absolute addressing if the Xtensa processor includes the absolute \*(C`L32R\*(C' addressing option. Otherwise, only the PC-relative \*(C`L32R\*(C' mode can be used.
Enable or disable automatic alignment to reduce branch penalties at the expense of some code density. The default is --target-align.
Enable or disable transformation of call instructions to allow calls across a greater range of addresses. The default is --no-longcalls.
Enable or disable all assembler transformations of Xtensa instructions. The default is --transform; --no-transform should be used only in the rare cases when the instructions must be exactly as specified in the assembly source.
The following options are available when as is configured for a Z80 family processor.
Assemble for Z80 processor.
Assemble for R800 processor.
Assemble undocumented Z80 instructions that also work on R800 without warning.
Assemble all undocumented Z80 instructions without warning.
Issue a warning for undocumented Z80 instructions that also work on R800.
Issue a warning for undocumented Z80 instructions that do not work on R800.
Treat all undocumented instructions as errors.
Treat undocumented Z80 instructions that do not work on R800 as errors.
gcc\|(1), ld\|(1), and the Info entries for binutils and ld.
Copyright (c) 1991, 92, 93, 94, 95, 96, 97, 98, 99, 2000, 2001, 2002, 2006, 2007 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.1 or any later version published by the Free Software Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-Cover Texts. A copy of the license is included in the section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R".