ARCHLEVEL
On amd64, controls the level of SIMD enhancements used. If this variable is set to an architecture level from the list below and that architecture level is supported by the processor, SIMD enhancements up to ARCHLEVEL are used. If ARCHLEVEL is unset, not recognised, or not supported by the processor, the highest level of SIMD enhancements supported by the processor is used.
A suffix beginning with ‘’: or ‘+’ in ARCHLEVEL is ignored and may be used for future extensions. The architecture level can be prefixed with a ‘’! character to force use of the requested architecture level, even if the processor does not advertise that it is supported. This usually causes applications to crash and should only be used for testing purposes or if architecture level detection yields incorrect results.
The architecture levels follow the AMD64 SysV ABI supplement:
scalar-
scalar enhancements only (no SIMD)
baseline-
cmov, cx8, x87 FPU, fxsr, MMX, osfxsr, SSE, SSE2
x86-64-v2-
cx16, lahf/sahf, popcnt, SSE3, SSSE3, SSE4.1, SSE4.2
x86-64-v3-
AVX, AVX2, BMI1, BMI2, F16C, FMA, lzcnt, movbe, osxsave
x86-64-v4-
AVX-512F/BW/CD/DQ/VL