riscemu1

Risc-v emulator in python.

Usage

riscemu [-h] [--options OPTIONS] [--syscall-opts SYSCALL_OPTS] [--instruction-sets INSTRUCTION_SETS] [--stack_size [STACK_SIZE]] [--flen [FLEN]] [-v] [--interactive] [--ignore-exit-code]

file.asm [file.asm ...]

Overview

This emulator contains:

-: RISC-V Assembly parser

-: RISC-V Assembly loader

-: Emulation for most parts of the basic RISC-V instruction set and the M and A extensions

-: Naive memory emulator

-: Basic implementation of some syscalls

-: A debugging environment

Options

--strict-whitespace: - Do not treat all horizontal whitespace as equivalent

--check-prefix: - Allows changing a default match keyword CHECK to an arbitrary keyword

--implicit-check-not: - Adds implicit CHECK-NOT check that works on every input line

--help: - Display available options

-h, --help

show this help message and exit --options OPTIONS, -o OPTIONS Toggle options. Available options are:

disable_debug:: Disable ebreak instructions

no_syscall_symbols:: Don't add symbols for SCALL_EXIT and others

fail_on_ex:: If set, exceptions won't trigger the debugger

add_accept_imm:: Accept "add rd, rs, imm" instruction (instead of addi)

unlimited_regs:: Allow an unlimited number of registers

libc:: Load a libc-like runtime (for malloc, etc.)

ignore_exit_code:: Don't exit with the programs exit code. --syscall-opts SYSCALL_OPTS, -so SYSCALL_OPTS --instruction-sets INSTRUCTION_SETS, -is INSTRUCTION_SETS Instruction sets to load, available are: RV32I, RV32M, RV32A, RV32F, RV32D, Zicsr, RV_Debug. All are enabled by default --stack_size [STACK_SIZE] Stack size of loaded programs, defaults to 8MB

--flen [FLEN]: hardware FLEN, either 32 or 64. Defaults to 64

-v, --verbose: Verbosity level (can be used multiple times)

--interactive: Launch the interactive debugger instantly instead of loading any programs

--ignore-exit-code: Ignore exit code of the program and always return 0 if the program ran to completion.