Verilog::Netlist::PinSelection3pm
Nets attached to a verilog cell's pins
Overview
Verilog::Netlist::PinSelection objects are used by Verilog::Netlist::Pin to define ranges of nets attached to the respective pin of a cell.
Accessors
- $self->netname
-
Name of the respective net, or, if use_pinselects is disabled, the string representation of the whole pin value. In the case of a sized constant only the part following the ' is stored while the width is encoded in the msb and lsb fields.
- $self->lsb
-
Least significant bit of the underlying net within the selection.
- $self->msb
-
Most significant bit of the underlying net within the selection.
Member functions
- $self->bracketed_msb_lsb
-
Returns the common string representation of a vectored net, e.g. netA[15:8].
Distribution
Verilog-Perl is part of the <https://www.veripool.org/> free Verilog EDA software tool suite. The latest version is available from CPAN and from <https://www.veripool.org/verilog-perl>.
Copyright 2000-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
Releases
4 releases since Debian 10 (Buster); the text changed 3 times.